1. Field of the Invention
This invention relates to clock-pulse-activated sampling and/or storage of signal information. More particularly, this invention relates to means for preventing distortion of the transferred data when the data input can change at a time which is close to the sampling time.
2. Description of the Prior Art
It is known that data alteration can occur in a clock-controlled signal sampling system if a change in input signal occurs too close in time to the active clock edge. The data alteration is caused by an abnormally long propagation delay within a storage device (such as a register) before the output of the storage data becomes valid; such abnormal propagation delay in turn is caused by meta-stable behavior within the device. The distortion may appear as an error in the device output (e.g. a zero rather than a one), or it may appear as an undue delay in the output data becoming valid.
Such data distortion can occur both for signal transitions preceding the clock edge as well as for transitions following the clock edge. That is, there is a timing "window" around the active clock edge within which a change in input signal will have a finite probability of causing an error in either stored data, or the data transferred to a downstream device.
FIG. 1 shows an exemplary application where such data distortion (sometimes referred to as data corruption) can occur. The apparatus of FIG. 1 is based on a prior art video sub-system such as shown in U.S. patent application Ser. No. 665,309 filed Mar. 6, 1991 by Denis O'Mahony (see for example FIG. 10 thereof). In such a system, the video signals for controlling a CRT are stored in a Frame Store 20 for subsequent transfer to a video RAM-DAC 22 forming part of an integrated-circuit (IC) chip. The data (I) is transferred from the Frame Store to a first flip-flop register 24 where it is clocked in by a signal identified as CLK1. This clock signal is developed by the clock logic 26 associated with the Frame Store 20 as part of the graphics board. The initially stored data then is transferred (Q) to a second flip-flop register 28 where it is clocked in by CLK2. This clock signal is derived from a pulse-frequency divider 30 activated by an external oscillator 32. The output of the divider also is directed to the clock logic 26 and is used among other things to generate CLK1.
Referring now also to FIG. 2, there is shown a timing diagram for CLKS 1 and 2, the signal information I and the signal Q at the output of the first flip-flop register 24. If the transition 34 in the signal Q occurs at any time falling within the shaded region 36 (covering a period from just before to just after CLK2), there will be a finite probability that the data delivered downstream by the second register 28 will be in error, or will be so delayed as to cause an error to occur in a downstream device.
As indicated in FIG. 2, the time period represented by the shaded area 36 consists of a first time Tsu preceding CLK2, and a second time Th following CLK2. Tsu is known as the "setup time", and Th is known as the "hold time". Tsu and Th are not necessarily equal. Any input signal transition occurring in either Tsu or Th will result in an abnormally extended propagation delay through the register, thereby possibly causing an error in a downstream device (e.g., RAM-DAC 22). If an input transition occurs before the setup time, or after the hold time, the propagation delay to the output will be normal, and the stored data will be valid.
The relationship between CLK1 and the input data (I) is such that the setup and hold times of the inputs to the first register 24 are satisfied. However, the delay between CLK1 and CLK2 is dependent on the actual circuit implementation of the clock logic 26. From the timing diagram of FIG. 2, there is a range of phase delay between CLK1 and CLK2 which will allow the input data to be synchronized and clocked through the RAM-DAC 22. However, there also is a range of phase delay between CLK1 and CLK2 where data corruption will occur.
Because the clock logic 26 is required to meet various timing requirements unrelated to the RAM-DAC 22, it is difficult for the graphics board designer to establish a proper phase delay between CLK1 and CLK2 such as to avoid errors due to distortion of the data stored in or output from the second register 28. This difficulty increases as the operating frequency increases. However, it has been found, in accordance with the present invention, to be possible to provide automatic control of the phase relationship between CLK1 and CLK2 after the graphics board has been assembled with the RAM-DAC 22 so as to assure proper time spacing between the CLK1 and CLK2 clock pulses and thereby avoid such data distortion.